[1] 许居衍,黄安君. 后摩尔时代的技术创新[J]. 电子与封装,2020,20(12):120101. XU Juyan,HUANG Anjun. Technological innovation in the post-Moore law period[J]. Electronics & Packaging,2020,20(12):120101. [2] 黄如,黎明,安霞,等. 后摩尔时代集成电路的新器件技术[J]. 中国科学:信息科学,2012,42(12):1529-1543. HUANG Ru,LI Ming,AN Xia,et al. New device technologies of integrated circuit in post-Moore era[J]. SCIENTIA SINICA Informationis,2012,42(12):1529-1543. [3] 黎明,黄如. 后摩尔时代大规模集成电路器件与集成技术[J]. 中国科学:信息科学,2018,48(8):963-977. LI Ming,HUANG Ru. Device and integration technologies for VLSI in post-Moore era[J]. SCIENTIA SINICA Informationis,2018,48(8):963-977. [4] 康劲,吴汉明,汪涵. 后摩尔时代集成电路制造发展趋势以及我国集成电路产业现状[J]. 微纳电子与智能制造,2019,1(1):54-64. KANG Jin,WU Hanming,WANG Han. Development trend of integrated circuit manufacturing in the post-Moore era and the current situation of China's integrated circuit industry[J]. Micro/nano Electronics and Intelligent Manufacturing,2019,1(1):54-64. [5] 孙玲,黎明,吴华强,等. 后摩尔时代的微电子研究前沿与发展趋势[J]. 中国科学基金,2020,34(5):652-659. SUN Ling,LI Ming,WU Huaqiang,et al. Frontiers and trends of microelectronics in post Moore era[J]. Bulletin of National Natural Science Foundation of China,2020,34(5):652-659. [6] SIVACHANDRA J,SUBRAMANIAN S L. Silicon-interconnect fabric for fine-pitch (≤ 10μm) heterogeneous integration[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2021,11(5):727-738. [7] ADEEL A B,SIVACHANDRA J,SAPTADEEP P,et al. Heterogeneous integration at fine pitch (≤ 10μm) using thermal compression bonding[C]//2017 IEEE 67th Electronic Components and Technology Conference (ECTC). IEEE,2017:1276-1284. [8] JOHN H L,CHENG T K,KAI M Y,et al. Panel-level fan-out RDL-first packaging for heterogeneous integration[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2020,10(7):1125-1137. [9] JOHN H L,GARY C F C,JONES Y C H,et al. Fan-out (RDL-first) panel-level hybrid substrate for heterogeneous integration[C]//2021 IEEE 71th Electronic Components and Technology Conference (ECTC). IEEE,2021:148-156. [10] CHENG T K,HENRY Y,JOHN H L,et al. Chip-first fan-out panel-level packaging for heterogeneous integration[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2018,8(9):1561-1572. [11] HOU S Y,HSIA H,TSAI C H,et al. Integrated deep trench capacitor in Si interposer for CoWoS heterogeneous integration[C]//2019 IEEE International Electron Devices Meeting (IEDM). IEEE,2019:19.5.1-19.5.4. [12] 方君鹏,王谦,郑凯,等. 面向异质集成的纳米修饰互连技术[J]. 微纳电子与智能制造,2021,3(1):89-97. FANG Junpeng,WANG Qian,ZHENG Kai,et al. Nano-modification interconnection technology for heterogeneous integration[J]. Micro/nano Electronics and Intelligent Manufacturing,2021,3(1):89-97. [13] Semiconductor Industry Association. International technology roadmap for semiconductors 2.02015 edition:Heterogeneous integration[R]. Washington DC:SIA,2015. [14] MING F C,FANG C C,WEN C C,et al. System on integrated chips (SoICTM) for 3D heterogeneous integration[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). IEEE,2019:594-599. [15] HOU S Y,CHEN W C,HU C,et al. Wafer-level integration of an advanced logic-memory system through the second-generation CoWoS technology[J]. IEEE Transactions on Electron Devices,2017,64(10):4071-4077. [16] YI C T,HAN W H,KUAN N C. Low temperature copper-copper bonding of non-planarized copper pillar with passivation[J]. IEEE Electron Device Letters,2020,41(8):1229-1232. [17] TZU C C,KAI M Y,JIAN C L,et al. Investigation of pillar-concave structure for low temperature Cu-Cu direct bonding in 3D/2.5D heterogeneous integration[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2020,10(8):1296-1303. [18] TZU C C,KAI M Y,JIAN C L,et al. Non-planarization Cu-Cu direct bonding and gang bonding with low temperature and short duration in ambient atmosphere[C]//2019 IEEE International Electron Devices Meeting (IEDM). IEEE,2019:5.5.1-5.5.4. [19] YU T Y,TZU C C,TING Y Y,et al. Low-temperature Cu-Cu direct bonding using pillar-concave structure in advanced 3-D heterogeneous integration[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2017,7(9):1560-1566. [20] AKASAKA Y. Three-dimensional IC trends[J]. Proceedings of the IEEE,1986,74(12):1703-1714. [21] CHEN M F,TSAI C H,KU T,et al. Low temperature SoIC bonding and stacking technology for 12-/16-Hi high bandwidth memory (HBM)[J]. IEEE Transactions on Electron Devices,2020,67(12):5343-5348. [22] ASISA K P,KUAN N C. Low temperature Cu-Cu bonding technology in three dimensional integration:An extensive review[J]. ASME Transactions,Journal of Electronic Packaging,2018,140(1):010801. [23] CHENG H L,YI L Y,CHIAO P C,et al. Adhesion properties of electroplating process between polyimide and metal layer for polymer/metal hybrid bonding[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2020,10(1):168-175. [24] MUDRICK J P,SIERRA-SUAREZ J A,JORDAN M B,et al. Sub-10μm pitch hybrid direct bond interconnect development for die-to-die hybridization[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). IEEE,2019:648-654. [25] GAO G L,MIRKARIMI L,FOUNTAIN G,et al. Scaling package interconnects below 20μm pitch with hybrid bonding[C]//2018 IEEE 68th Electronic Components and Technology Conference (ECTC). IEEE,2018:314-322. [26] LEE B,MROZEK P,FOUNTAIN G,et al. Nanoscale topography characterization for direct bond interconnect[C]//2019 IEEE 69th Electronic Components and Technology Conference (ECTC). IEEE,2019:1041-1046. [27] KIM S W,FODOR F,HEYLEN N,et al. Novel Cu/SiCN surface topography control for 1μm pitch hybrid wafer-to-wafer bonding[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC). IEEE,2020:216-222. [28] BOURJOT E,CASTAN C,NADI N,et al. Towards 5µm interconnection pitch with die-to-wafer direct hybrid bonding[C]//2021 IEEE 71th Electronic Components and Technology Conference (ECTC). IEEE,2021:470-475. [29] BEYNE E,KIM S W,PENG L,et al. Scalable,sub 2μm pitch,Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology[C]//2017 IEEE International Electron Devices Meeting (IEDM). IEEE,2017:32.4.1-32.4.4. [30] TAKEUCHI K,FUJINO M,SUGA T. Room temperature temporary bonding of glass substrates based on SAB method using Si intermediate layer[J]. IEEE Transactions on Components Packaging and Manufacturing Technology,2017,7(10):1713-1720. [31] LIU Z Y,CAI J,WANG Q,et al. Modified pulse laser deposition of Ag nanostructure as intermediate for low temperature Cu-Cu bonding[J]. Applied Surface Science,2018,445:16-23. [32] MU F W,HE R,SUGA T. Room temperature GaN-diamond bonding for high-power GaN-on-diamond devices[J]. Scripta Materialia,2018,150:148-151. [33] WU Z J,WANG Q,SONG C M,et al. Low temperature fine-pitch wafer-level Cu-Cu bonding using nanoparticles fabricated by PVD[C]//IEEE 68th Electronic Components and Technology Conference (ECTC). IEEE,2018:287-292. [34] LIU Z Y,CAI J,WANG Q,et al. Thermal-stable void-free interface morphology and bonding mechanism of low-temperature Cu-Cu bonding using Ag nanostructure as intermediate[J]. Journal of Alloys and Compounds,2018,767:575-582. [35] FANG J P,CAI J,WANG Q,et al. Low temperature Au-Au bonding using Ag nanoparticles as intermediate[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC). IEEE,2020:729-734. [36] OPPERMANN H,DIETRICH L,KLEIN M,et al. Nanoporous interconnects[C]//3rd Electronics System Integration Technology Conference (ESTC). IEEE,2010:1-4. [37] MORITA T,YASUDA Y,IDE E,et al. Bonding technique using micro-scaled silver-oxide particles for in-situ formation of silver nanoparticles[J]. Materials Transactions,2008,49(12):2875-2880. [38] OKADAA A,NIMURAA M,UNAMIA N,et al. Low temperature Au-Au flip chip bonding with VUV/O3 treatment for 3D integration[C]//20123rd IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D). IEEE,2012:171. |