• CN:11-2187/TH
  • ISSN:0577-6686

机械工程学报 ›› 2022, Vol. 58 ›› Issue (2): 166-175.doi: 10.3901/JME.2022.02.166

• 微纳连接新工艺 • 上一篇    下一篇

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纳米银微焊点阵列的超快激光图形化沉积及其芯片封装研究

吴永超1, 王帅奇2, 郭伟1, 刘磊2, 邹贵生2, 彭鹏1   

  1. 1. 北京航空航天大学机械工程及自动化学院 北京 100191;
    2. 清华大学机械工程系 北京 100084
  • 收稿日期:2021-05-03 修回日期:2021-10-14 出版日期:2022-01-20 发布日期:2022-03-19
  • 通讯作者: 彭鹏(通信作者),男,1985年出生,博士,副教授,博士研究生导师。主要从事激光加工、纳连接、焊接冶金、低温封装及水处理等方面的研究。E-mail:ppeng@buaa.edu.cn
  • 作者简介:吴永超,男,1992年出生,博士研究生。主要从事激光加工、脉冲激光沉积、纳米材料连接和芯片封装等方面的研究。E-mail:wuyongchao@buaa.edu.cn
  • 基金资助:
    国家自然科学基金(52075287)和国家重点研发计划(2017YFB1104900)资助项目。

Patterning Deposition of Nano-sliver Micro Bumps Array by Ultrafast Laser and Its Chip Packaging Research

WU Yongchao1, WANG Shuaiqi2, GUO Wei1, LIU Lei2, ZOU Guisheng2, PENG Peng1   

  1. 1. School of Mechanical Engineering & Automation, Beihang University, Beijing 100191;
    2. School of Mechanical Engineering, Tsinghua University, Beijing 100084
  • Received:2021-05-03 Revised:2021-10-14 Online:2022-01-20 Published:2022-03-19

摘要: 随着集成电路芯片封装向小型化、集成化方向的不断发展,无铅锡基钎料性能已不能满足目前集成电路封装的需求。本文提出了一种脉冲激光图形化沉积纳米金属颗粒制备小尺寸、细节距焊点阵列的工艺,用于替代集成电路芯片封装中传统锡基焊点。采用图形化沉积的纳米银焊点阵列连接Si芯片及覆铜陶瓷(DBC)基板来验证该工艺在集成电路倒装芯片封装中的可行性。结果表明,采用聚酰亚胺胶带作为掩膜,可成功沉积出特征尺寸100 μm的银焊点阵列,其最大高度50 μm且呈锥形形貌。焊点锥形形貌的主要形成原因是沉积过程中纳米颗粒在掩膜孔内壁积累造成掩膜孔径不断减小及掩膜孔深度阻碍了颗粒在孔边缘的沉积。在250℃-3 MPa-10 min的热压连接参数下,形成的焊点微观结构呈中心致密、边缘疏松状态。接头剪切强度随焊点沉积高度的增加而增加,当沉积高度为50 μm时,接头强度达到20 MPa以上,剪切断裂主要发生在银焊点与DBC基板的连接界面处,断裂方式为韧性断裂。

关键词: 脉冲激光沉积, 图形化封装, 银焊点阵列, 热压烧结, 剪切强度

Abstract: With the continuous development of integrated circuit chip packaging in the direction of miniaturization and integration, the performance of lead-free tin-based solder can no longer meet the current requirements. A novel technology of pulsed laser patterning deposition of metal nanoparticles is proposed to prepare small-sized and fine pitch bumps array, which is used to replace the traditional tin-based solder bumps in integrated circuit chip packaging. In order to verify the feasibility of this process in integrated circuit chip packaging, the patterning deposited nano-silver bumps array is used to connect Si chip and direct bonding copper (DBC) substrate. The results show that the silver bumps array with feature size of 100 μm can be deposited by PI tape mask successfully, with a maximum height of 50 μm and a tapered morphology. The tapered morphology is mainly attribute to the accumulation of nanoparticles on the inner wall of mask holes during deposition causing the decreasing of hole size and the depth of the mask hole hinders the deposition of nanoparticles on the bottom edge of the hole. Under the hot-press sintering parameters of 250℃-3 MPa-10 min, the joints are successfully prepared, with dense microstructure in the bumps center and loose in the edge. The shear strength of the joint increases with the deposition height of sliver bumps, and the strength reaches 20 MPa with a 50 μm bump height. The shear fracture mainly occurs at the interface between Ag bumps and DBC substrate, and the fracture mode is ductile fracture.

Key words: pulsed laser deposition, patterning packaging, sliver bumps array, hot pressed sintering, shear strength

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