[1] SHOREY A B,LU R. Progress and application of through glass via (TGV) technology[C]//Pan Pacific Microelectronics Symposium. IEEE,2016:1-6. [2] OKORO C,JAYARAMAN S,POLLARD S,Monitoring the effect of thermal shock on crack growth in copper through-glass via substrates[C/CD]//71st Proc.,Electronics Components and Technology Conference (ECTC),June 2021,San Diego,USA. [3] 陈力,杨晓锋,于大全. 玻璃通孔技术研究进展[J]. 电子与封装,2021,21(4):1-3. CHEN Li,YANG Xiaofeng,YU Daquan. Development of through glass via technology[J]. Electronics and Packaging,2021,21(4):1-3. [4] AHMED O,JALILVAND G,POLLARD S,et al. The interfacial reliability of through-glass vias for 2.5D integrated circuits[J]. Microelectronics International,2020,37(4):181-188. [5] 林来存. 三维玻璃通孔(TGV)关键工艺及无源器件集成研究[D]. 北京:中国科学院大学,2016. LIN Laicun. Research on the key processes of 3-Demensional through glass via and integrated passive devices[D]. Beijing:The University of Chinese Academy of Sciences,2016. [6] WANG B K,CHEN Y A,SHOREY A,et al. Thin glass substrates development and integration for through glass vias (TGV) with copper (Cu) interconnects[C]//2012 7th International Microsystems,Packaging,Assembly and Circuits Technology Conference (IMPACT),2012:247-250 [7] SHOREY A,POLLARD S,STRELTSOV A,et al. Development of substrates for through glass vias (TGV) for 3D-IC integration[C]//Electronic Components and Technology Conference (ECTC),2012 IEEE 62nd. IEEE,2012. [8] 张名爱. 应用于三维集成封装的玻璃转接板的制备和测试[D]. 南京:东南大学,2017. ZHANG Mingai. Study on optimized fabrication of glass interposer for 3D integration[D]. Nanjing:Southeast University,2017. [9] RYU S K,LU K H,ZHANG X,et al,Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D Interconnects[J]. IEEE Transactions on Device and Materials Reliability,2011,11(1):35-43. [10] LU K H,ZHANG Xuefeng,RYU S K,et al. Thermo-mechanical reliability of 3D ICs containing through silicon vias[C]//Electronics Components and Technology Conference (ECTC),May 2009,San Diego,CA. [11] BENALI A,FAQIR M,BOUYA M,et al. Analytical and finite element modeling of through glass via thermal stress[J]. Microelectronic Engineering,2016,151:16-18. [12] CHUKWUDI O. Thermo-mechanical characterization of copper through-silicon via interconnect for 3D chip stacking[D]. Belgium:Catholic University of Leuven,2010. [13] OKORO C,ENEMAN G,GONZALEZ M,et al. Analysis of the induced stresses in silicon during thermocompression Cu-Cu bonding of Cu-through- vias in 3D-SIC architecture[C]//57th Proc.,Electronics Components and Technology Conference (ECTC),June 2007,Reno,USA,2007:249-255. [14] OKORO C,YANG Y,VANDEVELDE B,et al. Extraction of the appropriate material property for realistic modeling of through-silicon-vias using μ-Raman spectroscopy[C]//International Interconnect Technology Conference. IEEE,2008:16-18. [15] OKORO C,LEVINE L E,XU R,et al. Synchrotron-based measurement of the impact of thermal cycling on the evolution of stresses in Cu through-silicon vias[J]. Journal of Applied Physics,2014,115(24):159-165. [16] OKORO C,LAU J W,GOLSHANY F,et al. A detailed failure analysis examination of the effect of thermal cycling on Cu TSV reliability[J]. IEEE Transactions on Electron Devices,2013,61(1):15-22. [17] WEI T,QIAN W,JIAN C,et al. Performance and reliability study of TGV interposer in 3D integration[C]//2014 IEEE 16th Electronics Packaging Technology Conference (EPTC),2014:601-605. [18] OKORO C,ALLOWATT T,POLLARD S. Resolving thermo-mechanically induced circumferential crack formation in copper through-glass vias[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC). IEEE,2021:954-958. [19] DEMIR K,OGAWA T,SUNDARAM V,et al. Reliability of through-package-vias from via-first processing with ultra-thin glass[J]. IEEE Transactions on Device and Materials Reliability,2017,17(4):683-691. [20] DEMIR K,ARMUTLULU A,SUNDARAM V,et al. Reliability of copper through-package vias in bare glass interposers[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology,2017,7(6):829-837. [21] DEMIR K,SUKUMARAN V,SATO Y,et al. Reliability of fine-pitch through-vias in glass interposers and packages for high-bandwidth computing and communications[J]. Mater. Sci.:Mater.Electron.,2018,29:12669-12680. [22] TOPPER M,NDIP I,ERXLEBEN R,et al. 3-D thin film interposer based on TGV (through glass vias):An alternative to Si-interposer[C]//2010 Proceedings 60th Electronic Components and Technology Conference (ECTC),2010:66-73. [23] 秦飞,王珺,万里兮,等. TSV结构热机械可靠性研究综述[J]. 半导体技术,2012,37(11):825-831. QIN Fei,WANG Jun,WAN Lixi,et al. Review on the thermal mechanical reliability of TSV structures[J]. Semiconductor Technology,2012,37(11):825-831. [24] SHOREY A B,LU R. Progress and application of through glass via (TGV) technology[C]//Pan Pacific Microelectronics Symposium. IEEE,2016:1-6. [25] LUECK M,HUFFMAN A,SHOREY A. Through glass vias (TGV) and aspects of reliability[J]. Proceedings- Electronic Components and Technology Conference,2015,2015:672-677. [26] CHENG H C,LI K H,CHENG Y S,et al. Characterization of the flexural strength and fatigue life of ultra-thin glass after dicing[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology,2018,8(12):2213-2221. [27] LEE C K,WANG J C,LIN Y M,et al. Reliability test for integrated glass interposer[C]//2016 International Conference on Electronics Packaging (ICEP),2016:48-51. [28] KURAMOCHI S,KUDO H,AKAZAWA M,et al. Glass interposer technology advances for high density packaging[C]//2016 IEEE CPMT Symposium Japan (ICSJ),2016:213-216. [29] KURAMOCHI S,KUDO H,AKAZAWA M,et al. Glass interposer technology advances for high density packaging[C]//2016 IEEE CPMT Symposium Japan (ICSJ),2016:213-216. [30] OKORO C,MAUREY P,POLLARD S. Time and temperature dependence of copper protrusion in metallized through glass vias (TGVs) fabricated in fused silicon substrate[J]. IEEE Transactions on Device and Materials Reliability,2021,21(1):129-136. [31] OKORO C,JAYARAMAN S,POLLARD S. Understanding and eliminating thermo-mechanically induced radial cracks in fully metallized through-glass via (TGV) substrates[J]. Microelectronics Reliability,2021,120:114092. [32] PARRY L,ASHCROFT I A,WILDMAN R D. Understanding the effect of laser scan strategy on residual stress in selective laser melting through thermo- mechanical simulation[J]. Additive Manufacturing,2016,12:1-15. [33] KANNOJIA H K,ARAB J,SIDHIQUE A,et al. Fabrication and characterization of through-glass vias (TGV) based 3D spiral and toroidal inductors by cost-effective ECDM process[C]//2020 IEEE 70th Electronic Components and Technology Conference (ECTC),2020:1192-1198. [34] AMRANI A E,BENALI A,BOUYA M,et al. A study of through package vias in a glass interposer for multifunctional and miniaturized systems[J]. Microelectronics Reliability,2014,54(9-10):1972-1976. [35] LIN Y J,HSIEH C C,YU C H,et al. Study of the thermo-mechanical behavior of glass interposer for flip chip packaging applications[C]//2011 IEEE 61st Electronic Components and Technology Conference (ECTC),2011:634-638. [36] CHEN Y,SU W,ZHANG P,et al. Failure analysis examination of the effect of thermal cycling on copper-filled TSV interposer reliability[C]//2018 19th International Conference on Electronic Packaging Technology (ICEPT),2018:148-151. [37] KUDO H,AKAZAWA M,YAMADA S,et al. High-speed high-density cost-effective Cu-filled through-glass-via channel for heterogeneous chip integration[C]//2019 International Conference on Electronics Packaging (ICEP),2019:104-109. [38] KUDO H,TAKANO T,AKAZAWA M,et al. High-speed,high-density,and highly-manufacturable Cu-filled through-glass-via channel (Cu bridge) for multi-chiplet systems[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC),2021:1031-1037 [39] CHEN Z,YU D,ZHANG M,et al. Development and reliability study of 3-D wafer level packaging for SAW filter using thin film capping[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology,2021,11(7):1047-1054. [40] HUANG T,CHOU B,SUNDARAM V,et al. Novel copper metallization schemes on ultra-thin,bare glass interposers with through-vias[C]//2015 IEEE 65th Electronic Components and Technology Conference (ECTC),2015:1208-1212. [41] WEI Tiwei,WANG Qian,CAI Jian,et al. Performance and reliability study of TGV interposer in 3D integration[C]//16th IEEE Proc.,Electronics Packaging Technology Conference (EPTC),Dec. 2014,Singapore,Singapore,2014:601-605. [42] SUKUMARAN V,CHEN Q,LIU F,et al. Through-package-via formation and metallization of glass interposers[C]//2010 Proceedings 60th Electronic Components and Technology Conference (ECTC),2010:557-563. [43] SUKUMARAN V,KUMAR G,RAMACHANDRAN K,et al. Design,fabrication,and characterization of ultrathin 3-D glass interposers with through-package-vias at same pitch as TSVs in silicon[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology,2014,4(5):786-795 [44] DE M K,RAMACHANDRAN K,SATO Y,et al. Thermomechanical and electrochemical reliability of fine-pitch through-package-copper vias (TPV) in thin glass interposers and packages[C]//2013 IEEE 63rd Electronic Components and Technology Conference,2013:353-359. [45] SHOREY A,COCHET P,HUFFMAN A,et al. Advancements in fabrication of glass interposers[C]//2014 IEEE 64th Electronic Components and Technology Conference (ECTC),2014:20-25. [46] CHIEN C H,LEE C K,YU H,et al. Performance and process comparison between glass and Si interposer for 3D-IC integration[J]. International Symposium on Microelectronics,2013,2013(1):000618-000624. [47] SRIDHARAN V,MIN S,SUNDARAM V,et al. Design and fabrication of bandpass filters in glass interposer with through-package-vias (TPV)[C]//2010 Proceedings 60th Electronic Components and Technology Conference (ECTC),2010:530-535. |