• CN: 11-2187/TH
  • ISSN: 0577-6686

Journal of Mechanical Engineering ›› 2024, Vol. 60 ›› Issue (19): 261-276.doi: 10.3901/JME.2024.19.261

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Review on the through Silicon Via Technology in the 3D-system in Package (3D-SiP)

WANG Meiyu1,2, ZHANG Haobo1, HU Weibo1, MEI Yunhui3   

  1. 1. School of Electronic Information and Optical Engineering, Nankai University, Tianjin 300350;
    2. Shenzhen Research Institute, Nankai University, Shenzhen 518000;
    3. School of Electrical Engineering, Tiangong University, Tianjin 300387
  • Received:2023-10-19 Revised:2024-03-04 Online:2024-10-05 Published:2024-11-27

Abstract: With the increasing complexity of the system, the traditional packaging technology can no longer meet the high-performance interconnection of multi-chips and multi-devices.3D-system in package (3D-SiP) achieves high-performance integration of chips and devices through multi-layer stacking and stereo interconnection.Among them, the through silicon via (TSV) structure plays a crucial role in 3D-SiP.This study systematically reviewed the TSV technology, including its technical background, manufacturing, bonding process and application features of TSV.In addition, it compared the advantages and disadvantages of different manufacturing processes and bonding processes, such as etching, laser drilling, deposited film and metal filling in manufacturing process, solder bump, copper pillar bump and hybrid bonding in bonding process, summarized the recent research progress and the current challenges, and prospected the development trend of TSV in the future.

Key words: 3D packaging, system in package(SiP), through silicon via(TSV), vertical interconnection

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