Abstract: Silicon epitaxial wafer is the basic functional material for large scale integrated circuits and semiconductor devices, etc. It is the growth of uniform epitaxial thin layer on single crystal silicon wafer through epitaxial reaction, the uniformity control of epitaxial layer's thickness and electrical resistivity is the key challenge of silicon epitaxial growth. The growth quality of silicon epitaxial layers is significantly influenced by the design of reaction chamber and thermal flow field. A multi-physics field simulation model to analyze the effects of chamber structure on the uniformity of thermal field distribution is established. Additionally, the effects of process parameters such as carrier gas flow rate, inlet gradient and susceptor speed on the silicon epitaxial growth reaction process through numerical simulation are investigated. Experimental results from multi-point temperature tests of reaction chamber demonstrate a high level of agreement between predicted and measured temperature distributions under different process conditions, with a maximum temperature prediction deviation < 1.2%. Based on the simulation analysis, an optimized combination of epitaxial growth reaction parameters is obtained, and then perform silicon epitaxial growth experiments on 200 mm wafers. The testing results show that a thickness inhomogeneity < 0.76% and an in-chip resistivity non-uniformity < 1.58%, satisfying the requirements for high quality in silicon epitaxial layer growth for integrated circuits.

Key words: silicon epitaxy layer, epitaxial growth, chemical vapor deposition, heat flow field, reaction chamber