Ultrasonic Phased Array Digital Beamformer Design Based on Multi-FPGA

doi:10.3901/JME.2016.02.070

Abstract

Abstract: As ultrasonic phased array technology develops, the number of supported channels in the system increases and the echo digitalization frequency gets higher. The massive data to be processed and transmitted in real time brought by the large number of supported channels and the high frequency of echo digitizer during inspection raise challenges in the digital beamformer design in ultrasonic phased array system. Therefore, a multi-core hardware based two-stage digital beamformer of using FPGA was designed and implemeted to process massive data in real time. System accuracy would be ensured by introducing the system synchronization mechanism. Also, high-speed serial bus was adopted for the transmission of massive data in real time. Test shows that the design can run at the condition of 64 channels and 200 MSPS digitalization frequency.

Key words: beamforming, high-speed serial bus, massive data, two-stage architecture

CLC Number:

TB51

CAI Mingfei, SHI Fangfang, KONG Chao, ZHANG Bixing. Ultrasonic Phased Array Digital Beamformer Design Based on Multi-FPGA[J]. Journal of Mechanical Engineering, 2016, 52(2): 70-75.

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